1. Field of the Invention
This invention relates to MOS-gated double-diffused semiconductor devices. Such devices include lateral and vertical DMOS transistors, IGBTs, MOS-controlled thyristors (MCT's) and any Mos-geated Mos-controlled device formed using DMOS technology, whether as a discrete device, or as a device incorporated in an integrated circuit. More specifically, the invention relates to a method of fabricating such devices using two layers of polysilicon, one layer of which is the gate electrode and a second layer overlying and insulated from the gate electrode which second layer serves as a source of dopant for one or more of the device regions and also serves as an electrical contact to that (those) region(s). In addition, components such as resistors, capacitors, diodes, and thin film transistors can be simultaneously fabricated using this second layer of polysilicon.
2. Description of the Prior Art
DMOS (double-diffused MOS) devices using gate electrodes of polysilicon (polycrystalline silicon) are well known in the art and are conventionally fabricated using multiple cells or repetitive interdigitated structures on a die by forming various layers (see FIG. 1) in and on an epitaxial (epi) layer 6 which is doped N- and formed on a silicon crystal substrate 8 doped N+. Typically, a polysilicon (polycrystalline silicon) gate layer 10 is formed on an underlying gate oxide layer 12 to serve as a gate electrode. (All figures in this disclosure are cross-sectional views of a portion of a semiconductor wafer or die). Source regions 14 and a body region 16 (including a P+ body region 18) are diffused into epi layer 6. P+ body region 18 is shown in FIG. 1 as being both more heavily doped than the P-type body region and deeper than the body region. Region 18 only needs to be more heavily doped than the body region; it does not need to be deeper. Source 14 and body 16 regions are then both electrically contacted by depositing conductive material 20 in the area between gates of adjacent cell. Also, a conductive drain contact 22 is established on the underside of the substrate 8 (or on the top surface of the device if it is in an integrated circuit.)
In this structure disadvantageously the area devoted to the source and body contact 20 between gates 10 requires a certain amount of surface area on the epi layer 6 so as to be properly spaced from the gates 10. This is shown by the conventional contact alignment tolerance "d". Thus these devices have larger surface area than is otherwise necessary. It is well known that for such devices manufacturing cost is a function of surface area. Thus it is desirable to have a more compact power device structure than is available in the prior art by reducing the surface area devoted to the source contact regions.